Standard cells library layout development and verification

Abstract

Producing designs based on nano technologies at a cheap cost has always been a constant challenge for foundries. As we decrease the technology, hardware complexity increases due to increase in layout complexity. Different Integrated Circuit (IC) strategies have been adopted to decrease the time taken to design and lower fabrication costs. One of the methods to reduce cost is to use a ‘Standard Cell-Based’ IC implementation using Standard Cell Libraries. Standard Cells are the important building blocks of a modern semi-custom IC design. A Standard Cell Library consists of more than thousand different kinds of cells of various drive strengths. Standard Cell Libraries vary from Foundry to Foundry. The important factors that contribute for a good Standard Cell Library is PPA i.e., Power, Performance, Area which are very important in modern IC design. Modern IC’s are Required to perform very high computation that consumes less power in a handheld device. In this project I have been part of the development of standard cell library, Validation and its improvement in key factors like Area. In this report, I am presenting the development of some layouts of CMOS Standard Cell Library layout design using custom complier with different cell checks, and details of some cell check jobs that validates the layout. This project mainly focuses on generating the comprehensive library cells containing the cell layouts with various functionality of the cells.