Certification of Macros and Memories for VLSI in Nanometer Technology

Abstract

In the domain of deep submicron (DSM) and nanometer ASIC technologies (180 nm and below), the traditional separation between logical (synthesis) and physical (place and route) design methods often causes a problem—designs cannot meet their realistic timing objectives; creating the well known “timing closure problem”. Timing closure is now considered the biggest area of difficulty for ASIC performance-oriented designs. The underlying reason is that circuit delays are dominated by net delays, which are influenced by the placement of the cells. The traditional fanout-based wireload models, for estimating interconnect delay during synthesis, are considered inaccurate and are the key factor causing the lack of timing predictability between post synthesis and post layout results. It is evident that synthesis and placement technologies must merge to create properly placed and routable designs that meet realistic performance goals. This thesis described Certification of different libraries. Hereby Certification flow and issues faced during Certification are discussed. Certification of libraries is defined as the process of certifying an Intellectual Property (I.P.) through various design flows. Inputs to the certification process are the cell views available in libraries. These cell views are schematic, layout, symbol and abstract of the various combinational and sequential logic blocks. To make logical design CORE library is also required. The process starts by generating a gate level netlist using the cells available in the library to be certified. Next, the place and route flow operations like floorplanning, placement, clock tree synthesis (CTS), post CTS optimization, routing and post-route optimization are performed on this netlist to generate the layout at each and every level of flow. Ultimately, the post-routed design is fed to the finish design flow, wherein, the gdscad file (GDS-II) is generated along with some other files which are useful for the signoff flow of the design. By Signoff, one can do the operations like Formality Verification, DRC, LVS, Delay Calculation, Timing Analysis, Back-annotation and many more. The aim of certification is to verify that the libraries when used won’t create violations regarding timing closure, area constraints.