RTL Design of Risc Processor for DSP Application

Abstract

In order to achieve better performance of processor, we should strive to achieve a situation where most of the featured instructions are executable in a single cycle. Ideally, we would like to see a streamlined and uniform handling of all instructions, where the fetch and the execute stages take up the same time for any instruction, desirably, a single clock. This is basically one of the first and most important principles inherent in the RISC design. The RISC has attributes like Simple instructions, less complexity, Compiler generates software routines to perform complex instructions, and Instruction size is constant

The project aims at providing RTL Design of RISC processor for DSP application, which may be implemented on FPGA.

Various processor cores like ARM processor NIOS_II processor, PowerPC etc. are available in market which is widely acceptable by industries. These processors are available in form of Soft IP core module.

The project work includes detailed literature survey of ARM processor, NIOS_II processor, PowerPC. Comparison of these processors is carried out based on various parameters like Performance, Code density, Strength of instruction set, Supports by software tools, Interrupt mechanism etc.

In this work, 32-bit processor is designed using VHDL. The designed processor supports 32 various instructions. It supports all general addressing modes. The functionality of the designed is verified by writing a program to transfer a block of data in memory.