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DC Field | Value | Language |
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dc.contributor.author | Patel, Manish U. | - |
dc.date.accessioned | 2007-10-08T06:05:01Z | - |
dc.date.available | 2007-10-08T06:05:01Z | - |
dc.date.issued | 2007-06-01 | - |
dc.identifier.uri | http://hdl.handle.net/123456789/134 | - |
dc.description.abstract | Structured ASIC is very latest concept in the field of Configurable Logic. It bridges the gap between FPGA and Standard Cell based Design hence having advantages of both. With an optimized and programmable structure, the structured ASIC technology indeed introduces a dramatically reduce ASIC cost and manufacturing turn-around time. The structured ASIC implementation flow is more complex than the conventional cell-based flow. This project explore the differnt Structured ASIC architecture and Implement variuos designs on available Structured ASIC core like eASIC, ViASIC and LightSpeed hence customer can get best option for their Silicon Implementation. This report compares eASIC, ViASIC and LIghtSpeed architecture goodness using experimental techniques. Comparison is made with respect to each other in terms of frequency, utilization and capacity. As the design flow is complex various design issues encountered during the flow which may not occur in the ASIC flow. These issues are discussed and remedies for the same also proposed. | en |
dc.language.iso | en_US | en |
dc.publisher | Institute of Technology | en |
dc.relation.ispartofseries | 05MEC012 | en |
dc.subject | EC 2005 | en |
dc.subject | Project Report 2005 | en |
dc.subject | EC Project Report | en |
dc.subject | Project Report | en |
dc.subject | 05MEC012 | en |
dc.subject | 05MEC | en |
dc.subject | VLSI | - |
dc.subject | VLSI 2005 | - |
dc.title | Structured ASIC: Evaluation and Implementation | en |
dc.type | Dissertation | en |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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05MEC012.pdf | 05MEC012 | 2.11 MB | Adobe PDF | ![]() View/Open |
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