Study and Design of NVM Standard Cell Library

Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/136

Full metadata record

DC Field	Value	Language
dc.contributor.author	Thakkar, Rakesh A.	-
dc.date.accessioned	2007-10-08T06:27:16Z	-
dc.date.available	2007-10-08T06:27:16Z	-
dc.date.issued	2007-06-01	-
dc.identifier.uri	http://hdl.handle.net/123456789/136	-
dc.description.abstract	The goal of this project is to develop a library of cells for 0.35u ST process. The library developed is a general purpose low power library that can be put into any desired requirement for Digital Applications such as Smart Cards IC’s, automotive. The design methodology involves designing layouts from given schematics with specified width and length parameters. The key stress in designing the cells lies in minimizing the area occupied by each cell as the need of the designs is to maximize the number of transistors on the same area. The cells designed in the library included NAND INVERTERS HALF ADDER FULL ADDER BUFFERS NOR AOI MULTIPLEXERS COMBINATIONAL CIRCUITS	en
dc.language.iso	en_US	en
dc.publisher	Institute of Technology	en
dc.relation.ispartofseries	05MEC016	en
dc.subject	EC 2005	en
dc.subject	EC Project Report	en
dc.subject	Project Report 2005	en
dc.subject	Project Report	en
dc.subject	05MEC016	en
dc.subject	05MEC	en
dc.subject	VLSI	-
dc.subject	VLSI 2005	-
dc.title	Study and Design of NVM Standard Cell Library	en
dc.type	Dissertation	en
Appears in Collections:	Dissertation, EC (VLSI)

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