Design and Implementation Of Complete Test Set Generator using ATPG and Fault Coverage

Abstract

The amount of data required to test ICs is growing rapidly in each new generation of technology and achieving high test quality in ever smaller geometries requires more test patterns targeting delay faults and other fault models beyond stuck at faults. Conventional external testers have limited speed, memory, and I/O channels. It is often the bottleneck determining how fast you can test the chip. The varieties of ATPGs are currently available in the market. But to overcome the above said limitations, it requires an optimization or modification in current ATPGs. New ATPG can also be designed. So in this paper, we have presented a base of future research work on this direction. It contains the design and implementation of complete test set generator for combinational circuit using OOPS methodology. First it determines the required test for each fault in deterministic way. It computes the complete test set on basis of fault coverage for each test set and gets optimized complete test set for given circuits. The results of this tool for a standard ISCAS circuit c17 are presented in this paper.