Design and Implementation Of Gaussian Random Number Genrator in FPGA for Fixed-Point Architecture

Abstract

This paper presents hardware implementation of the randor1 number generator. Modified Box-Muller algorithm is preser ed here. Box-:\luller algorithm is used when Floating Point Arith etic units are available. Modified algorithm is used when Fixed Point as well as Floating-Point arithmetic units are available. This paper includes Architecture and implementation of l\Ioditled Box-Muller Algorithm in FPGA. Two 12-bit random A numb,rs are generated every clock cycle. Implementation of this .algorithm on Xilinx Spartan 2E XC2S~OOE FPGA occupies 1187 slices'119 block RAl\Is and 2206 LUTs. This implementation can gener~te 56 m~llion random numbers per second at a clock speed ~f 28 l\IHz. This Random Number Generator can be used In simul.tions. in CDl\IA technology to generate random code. in Encryption and Authentication algorithm as a random number generptor. Design offull range Uniform random J1umber generator and li~rdware architecture of Square root unit are also included. , IndexITerms-Box-Muller algorithm. CDMA Technology, FPGA Implementation, Gaussian Random Number Generator (GRNG). Hard\vare Design, Security, Simulations, Square Root Unit, Uniform RNG (URNG).