Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/150
Title: Study and Implementation of BIST for 65NM High Speed Memory
Authors: Choubey, Keerti
Keywords: 04MEC005
04MEC
EC 2004
EC Project Report
Project Report 2004
Project Report
VLSI
VLSI 2004
Issue Date: 1-Jun-2006
Publisher: Institute of Technology
Series/Report no.: 04MEC005
Abstract: In today’s era of System on Chip (SoC) a custom chip is composed of different embedded modules such as microprocessor, analog and mixed signal logic, digital logic and of course the integral part of all i.e. memories. More than 50% of all the designs today have embedded memories implemented in them which cover up more than 60% of total die area. While embedded memory presents significant system performance and cost reduction advantages, it also brings its own testing issues. Test vector style are not suitable for verifying embedded memory arrays, as they are too costly because of the time spent in the manufacturing tester grows exponentially as the embedded memory die area increases. This problem can be alleviated by implementing embedded memory built in self-test (BIST). In simplistic terms Memory BIST is an on-chip utility that enables the execution of a proven set of algorithmic style verification tests directly on the memory array. These tests can be executed at the design’s full operating frequency to prove the memory array operations and identify errors caused by chip defects. This thesis work consists of study and development of Memory BIST for memories of different size and types. Analysis and modification work is done on new shared BIST architecture for multiple memories. The analysis has proved that the new BIST architecture greatly improves the speed performance of the BIST while reducing the area. Study of BIST compiler development through C programming and shell scripting in UNIX environment has been done to support the team for compiler development. Major development work has been carried out on dedicated BIST for 65nm high speed Single- Port SRAM memory. After the insertion of BIST into the design, validation of new design is done which includes simulation, synthesis, gate simulation, formal equivalence check between different levels of RTL, and code coverage analysis. For the automation of these validation tasks a tool has been made using the shell programming in UNIX environment. The updation of the shell script of this tool is a part of this project work.
URI: http://hdl.handle.net/123456789/150
Appears in Collections:Dissertation, EC (VLSI)

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