Design and Implementation of Morphological Operations for Image Processing Applications

Abstract

The objective of this work is to design median filtering and morphological operations (dilation and erosion) for image processing applications using rank-order filter and implementing the same on FPGA. From these basic morphological operations, other operations such as opening, closing and edge-detection are implemented. Thresholding is done after the edge detection. The reason for doing hardware implementation is to improve the performance as software processing is comparatively time-consuming task. All these functions are implemented using 3 x 3 and 5 x 5 structuring element. Combined moving window architecture is also designed to select between 3 x 3 and 5 x 5 structuring element with resource sharing. Data size can be either 8-bits or 16-bits. Simulation and synthesis for image sizes up to 2048 x 2048 have been successfully done and frame-rate required for digital video image processing is achieved. For the implementation of rank-order filter, merge-sort sorting architecture and moving-window architecture is designed for both 3 x 3 and 5 x 5 structuring element. In this architecture, a 256 x 16-bits and 256 x 8-bits synchronous FIFO is designed so as to reduce the numbers of logic block utilization by using BlockRAMs available in target FPGA. Comparison of logic blocks utilization using synchronous and asynchronous FIFO, 3 x 3 and 5 x 5 structuring elements, and data width of 8-bits and 16-bits have been done. Image-to-file conversion routine is written in software for processing the image in VHDL code. Similarly file-to-image conversion routine is written in software for viewing the processed image.