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dc.contributor.authorDhare, Vaishali Hitesh-
dc.date.accessioned2010-06-12T04:14:57Z-
dc.date.available2010-06-12T04:14:57Z-
dc.date.issued2010-06-01-
dc.identifier.urihttp://hdl.handle.net/123456789/1546-
dc.description.abstractTo test the functioning of IC in today's era, Automatic Test Pattern Generator (ATPG) is becoming increasingly important as designs become more complicated. Keeping the structural fault coverage high while maintaining an acceptable design overhead is critical, it is important to achieve a high level of reliability with minimum cost and time. ATPG is bene cial in many ways. First, it can reduce the test time for a large circuit. In addition, ATPG can provide at speed, in system testing of the Circuit-Under-Test (CUT). This is a crucial component for the quality of testing. Single stuck at fault model is considered through out this project. Considering single stuck at fault, the fault list becomes lengthy as circuit -under- test (CUT) has large number of nets, to reduce the number of faults, fault equivalence method is used. Testability measures like controllability- 0, controllability -1 and Observability are considered to nd how complicated is to test internal nodes. Testability measures are controllability and observability. Controllability guides the test generation algorithms while setting a value to primary input (PI) in line justi cation problem. Actual gen- eration of test vector for every fault involves line activation step \line justi cation" and error propagation up to primary output .The codes are developed using C++ language for 2-fanin-fanout , and upto 10 fanin-fanout gates. The all programs are generic and can be used for any combinational circuit upto 10-fanin-fanout gate. An ecient and simple technique for test pattern generation is necessary with the intension of reducing number of faults and with use of testability measures along with advanced algorithm. This algorithm must be simple. In this project combinational ATPG is developed based on testability measures, FAN algorithm with reduced fault directory using fault equivalence. The proposed algorithm-modi ed FAN for genera- tion of test vectors is simple and can be used as an open source for academicians. The test vectors generated by advanced ATPG is compressed .The compression pro- gram is developed using C++ language.en
dc.language.isoen_USen
dc.publisherInstitute of Technologyen
dc.relation.ispartofseries08MEC003en
dc.subjectEC 2008en
dc.subjectProject Report 2008en
dc.subjectEC Project Reporten
dc.subjectProject Reporten
dc.subjectEC (VLSI)en
dc.subjectVLSIen
dc.subject08MECen
dc.subject08MEC003en
dc.subjectVLSI-
dc.subjectVLSI 2008-
dc.titleDesign And Implementation Of Advanced ATPG Generating Compressible Test Vectoren
dc.typeDissertationen
Appears in Collections:Dissertation, EC (VLSI)

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