Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/1546
Title: Design And Implementation Of Advanced ATPG Generating Compressible Test Vector
Authors: Dhare, Vaishali Hitesh
Keywords: EC 2008
Project Report 2008
EC Project Report
Project Report
EC (VLSI)
VLSI
08MEC
08MEC003
VLSI
VLSI 2008
Issue Date: 1-Jun-2010
Publisher: Institute of Technology
Series/Report no.: 08MEC003
Abstract: To test the functioning of IC in today's era, Automatic Test Pattern Generator (ATPG) is becoming increasingly important as designs become more complicated. Keeping the structural fault coverage high while maintaining an acceptable design overhead is critical, it is important to achieve a high level of reliability with minimum cost and time. ATPG is bene cial in many ways. First, it can reduce the test time for a large circuit. In addition, ATPG can provide at speed, in system testing of the Circuit-Under-Test (CUT). This is a crucial component for the quality of testing. Single stuck at fault model is considered through out this project. Considering single stuck at fault, the fault list becomes lengthy as circuit -under- test (CUT) has large number of nets, to reduce the number of faults, fault equivalence method is used. Testability measures like controllability- 0, controllability -1 and Observability are considered to nd how complicated is to test internal nodes. Testability measures are controllability and observability. Controllability guides the test generation algorithms while setting a value to primary input (PI) in line justi cation problem. Actual gen- eration of test vector for every fault involves line activation step \line justi cation" and error propagation up to primary output .The codes are developed using C++ language for 2-fanin-fanout , and upto 10 fanin-fanout gates. The all programs are generic and can be used for any combinational circuit upto 10-fanin-fanout gate. An ecient and simple technique for test pattern generation is necessary with the intension of reducing number of faults and with use of testability measures along with advanced algorithm. This algorithm must be simple. In this project combinational ATPG is developed based on testability measures, FAN algorithm with reduced fault directory using fault equivalence. The proposed algorithm-modi ed FAN for genera- tion of test vectors is simple and can be used as an open source for academicians. The test vectors generated by advanced ATPG is compressed .The compression pro- gram is developed using C++ language.
URI: http://hdl.handle.net/123456789/1546
Appears in Collections:Dissertation, EC (VLSI)

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