Automatic RTL generation for IO test Solution

Abstract

The ever-increasing competition in the semiconductor industry requires the de-velopers to reduce the design-to-market time of their products continuously. Alongwith adding more advanced features in the products, it is also important to take carethat the development process is fast, and the accuracy maintained. Automation ofvarious processes is thus imperative in saving time and helping designers expeditetheir design ow.Today, the I/O structures require the greatest amount of circuit design expertisealong with detailed process knowledge. It is the I/O element which nally interfacesthe core signal to the o-chip environment. Thus however ecient the core designmay be, it is the I/Os which determine the eciency of the chip. It is very importantto ensure that the designed I/O is functional and works well within the specications.Due to the large no. of input and output pins their must be protocol and automationis required.The functional verication of I/O 's can be done through JTAG IEEE 1149.1,but as the number of I/O's changes since for dierent Core Logic the I/O cells aredierent in number the whole design of implementation changes .So there is need ofthe completely automated and along with the characterization ow. The dierentsteps of the ow were automatic but run serially by the user. After each step the userhad to check the operation specic log les. These log les are checked for a specicresult and then the user proceeds.