High Speed Low Jitter CMOS Clock Recovery Circuit Design using PLL

Abstract

The concept of clock recovery nds wide applications in high speed digital data streamcommunication. In optical communication, for example, random data is sent over abre without any accompanying clock. But a synchronous data reception is essentialat the receiver side. Clock recovery is a phenomenon that deals with extracting theclock timing information out of the random data received, at the receiver side in highspeed data communication.This thesis presents a method for the design of self-biased High Speed CMOS ClockRecovery Circuit for NRZ data transmission using the concept of Phase-Locked Loops(PLL). A PLL design for the application of clock recovery has been realized using65 nm CMOS technology. The application targets clock recovery at speed of 1Gbps-2Gbps range. The total power dissipation observed is 4.7 mW using 1V power supply.The jitter is reduced using the Phase Detector design with dead-zone compensationand Charge Pump with minimum mismatch in the up and down currents. The VCOused in the circuit is purely dierential in nature and devoid of tail current. Boththe factors contribute to the reduction in noise in the circuit. Further a half-ratephase detector has been presented in order to compare the performance in terms ofjitter & power dissipation of the half-rate & full-rate (conventional) clock-recoveryarchitectures. The design simulation recovered clock results agree fairly well with theexpected results.