Development and Verification of eDRAM behavioral models

Abstract

As process of fabrication technologies advances, chip complexity increases and the design ow becomes more iterative. Iterations in the design ow cost money, time and engineering resources that adversely a ect the time to market and cost of the devices being designed. Veri cation dominates most chip development schedules, with electronic rms pouring up to 70 This report deals with the development of a generic veri cation environment of HDL models and describes the validation process and need for automation of valida- tion environment of Memories (SRAM and DRAM) behavioral models. The project deals with Development of eDRAM behavioral models and writing Testbench in Verilog to validate those behavioral models and using Shell Scripts to automate the validation process. NOTE: Since the work done in this project is of con dential nature, more stress is given on concepts than on actual work done