Design of FPGA based Co-Processor for Stereo Imaging Algorithms using Handel-C

Abstract

Computer manipulation of images is generally defined as Digital Image Processing (DIP). DIP is employed in variety of applications, including video surveillance, target recognition, and image enhancement. These are usually implemented in software but may also be implemented in special purpose hardware to meet timing constrains. FPGAs are often used as implementation platforms for real-time image processing applications because their structure is able to exploit spatial and temporal parallelism. Such parallelization is subject to the processing mode and hardware constraints of the system. These constraints can force the designer to reformulate the algorithm. This thesis represents some general techniques for dealing with the various constraints and efficient mappings for various image processing algorithms on parallel hardware. In this work the Fourier transform operation on image has been proposed using hybrid architecture of DSP and FPGA to achieve high throughput and to reduce processing time for the same. Hybrid architecture has been developed using reconfigurable architecture and hardware is modeled using a C-like hardware language called Handle-C. The proposed architecture is capable of producing one complex multiplication (Fixed point and Floating point) on every clock cycle. The hardware modeled was implemented using the DK4 Design Suite on the Xilinx Spartan 1500L FPGA. Another part of work focuses on development of Stereo Image Matching Algorithm named as Hierarchical Image Matching on the Spartan Xilinx Spartan 4000L FPGA. This includes implementation of Image Correlation block and Square root block using CORDIC algorithm. The algorithm was tested on standard image processing benchmarks and significances of the result are discussed