Design and Implementation of Sigma Delta DAC

Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/2048

Full metadata record

DC Field	Value	Language
dc.contributor.author	Mehta, Usha	-
dc.contributor.author	Patel, Jayesh	-
dc.date.accessioned	2011-03-26T09:36:21Z	-
dc.date.available	2011-03-26T09:36:21Z	-
dc.date.issued	2006-11-30	-
dc.identifier.citation	NUCONE - 2006 Institute Of Technology, Nirma Univeristy, Ahmedabad, November 30 - December 2, 2006, Page No. 1-4	en
dc.identifier.uri	http://hdl.handle.net/123456789/2048	-
dc.description.abstract	This paper presents a reconfigurable sigma-delta Digital-to-Analog Converter (DAC) which is suitable for embedded FPGA applications. The Sigma-Delta Modulator (SDM) design can be configured as a 3rd or5th order SDM for input word length of 8-bit. The converter (DAC) presented here is designed for sampling frequency of 10.2 KHz. and operates from a single 5V supply. The DAC presented in this paper having front end design is in VHDL code as well as in Verilog Code. Such DAC has many applications in field of Audio and Video	en
dc.relation.ispartofseries	ITFEC010-2	en
dc.subject	FPGA	en
dc.subject	DAC	en
dc.subject	Modulator	en
dc.subject	Sigma Delta	en
dc.subject	EC Faculty Paper	en
dc.subject	Faculty Paper	en
dc.subject	ITFEC010	en
dc.subject	IDFEC002	en
dc.title	Design and Implementation of Sigma Delta DAC	en
dc.type	Faculty Papers	en
Appears in Collections:	Faculty Papers, EC

Files in This Item:

File	Description	Size	Format
ITFEC010-2.pdf	ITFEC010-2	147.8 kB	Adobe PDF	View/Open

IR @ Nirma University