IR @ Nirma University
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http://10.1.7.192:80/jspui/handle/123456789/2048| Title: | Design and Implementation of Sigma Delta DAC |
| Authors: | Mehta, Usha Patel, Jayesh |
| Keywords: | FPGA DAC Modulator Sigma Delta EC Faculty Paper Faculty Paper ITFEC010 IDFEC002 |
| Issue Date: | 30-Nov-2006 |
| Citation: | NUCONE - 2006 Institute Of Technology, Nirma Univeristy, Ahmedabad, November 30 - December 2, 2006, Page No. 1-4 |
| Series/Report no.: | ITFEC010-2 |
| Abstract: | This paper presents a reconfigurable sigma-delta Digital-to-Analog Converter (DAC) which is suitable for embedded FPGA applications. The Sigma-Delta Modulator (SDM) design can be configured as a 3rd or5th order SDM for input word length of 8-bit. The converter (DAC) presented here is designed for sampling frequency of 10.2 KHz. and operates from a single 5V supply. The DAC presented in this paper having front end design is in VHDL code as well as in Verilog Code. Such DAC has many applications in field of Audio and Video |
| URI: | http://hdl.handle.net/123456789/2048 |
| Appears in Collections: | Faculty Papers, EC |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ITFEC010-2.pdf | ITFEC010-2 | 147.8 kB | Adobe PDF |  View/Open |
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