Impact of Scaling on Power Analysis in ASIC Design

Abstract

Power is considered to be the major limiter to the faster and more complex Application Specific Integrated Circuits (ASIC). Designing an ASIC in today’s deep submicron geometries is harder than ever, and the problems continue to worsen with shrinking geometries. In order to address this challenge, a combination of process, circuit design and microarchitecture changes are required. Consequently, to focus the optimization efforts in the right direction, authors have analyzed the effectiveness of an energy reduction mechanism that employs voltage scaling. Effect of technology variation on power dissipation is also highlighted. Mentor Graphics tools are used for this analysis. Among the various abstraction levels, analysis is carried out at the transistor level which leads to reasonable accuracy.