IP Quality Improvement Using Spyglass

Abstract

Time to market & Power is becoming a critical design criterion for ASIC/SoC de- signers. Early Design Analysis nd the issues which can pin points structural ,coding & consistency problem at RTL. Early Design Analysis can nd most comprehensive design problems related to clock, reset & CDC(clock domain crossings) which cannot nd in the veri cation of the design but this captures at the netlist level which will cause a design respin & TTM will increase. Early Design analysis nds such issues at RTL level, so it reduces the design respin time. To generate the netlist from the RTL designer needs the synthesis constraints. These constraints need to be accurate for the quality netlist. Early Design Analysis also helps to nd fault in the synthesis con- straints. Now Early Design Analysis also helps to generate the synthesis constraints automatically with the tool. This automation reduces the human e orts to generate constraints & generated constraints will have more accuracy. To meet power require- ment of the design it is likely to have power estimation at the RTL level itself, so the designer can apply di erent techniques at RTL level to meet power requirement when chip will manufactured. During this thesis, work based on the di erent steps of Early Design Analysis will be carried out on the di erent IP's with the the tool named SPYGLASS. Spyglass will observed problems related with the di erent IP's & will ensure that applied solution is feasible or not for the design at every stage of the Early Design Analysis. Also the comparision of the results will be performed for the features like constraints generation & power estimation will be carried out with some standard results.