Artificial Intelligence Based Test Data Compression Techniques

Abstract

The circuit consumes more power during test mode compared to functional mode. So test power has been major big concern in large System-on-Chip designs from last decade. In the rst part of report, the state-of-the-art in low power testing is presented. The rst part contains the detailed survey on various power reduction techniques proposed for both the aspects of testing i.e. external testing as well as Built-In-Self-Test. The advances in DFT techniques emphasizing low power is also included in this part. In the second part novel methods are presented which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the Hamming Distance between successive test vectors. In this method the test vectors are reordered for minimum total hamming distance and the same vector set is used for testing. Artificial intelligence is another approach that is described to reduce switching activity. Also Test power has become a serious problem with scan-based testing. It can lead to prohibitive test power in the process of test application. During the process of scan shifting, the states of the ipops are changing continually, which causes excessive switching activities. Test vector reordering for reducing scan in scan out power is one of the general goal of low power testing. WTM based reordering technique have proposed here to reorder the test vectors in an optimal manner to minimize switching activity during testing. In the third part it is shown that MT Fill algorithm is preferable when power is a big concern. Frequency directed bit lling approach is preferable when compression is a major goal. But the proposed approach that is a combination of MT ll and frequency directed bit lling is preferable when one wants to achieve moderate power and compression. The nal part addresses error-resilience that is the capability to tolerate bitips in a compressed test data stream (which is transferred from an Automatic Test Equipment (ATE) to the Device-Under-Test (DUT)). In an ATE, bitips may occur in either the electronics components of the loadboard, or the high speed serial communication links (between the user interface workstation and the head). It is shown that errors caused by bit- ips can seriously degrade the test quality (as measured by coverage) of the compressed data streams. The e ects of bit- ips on compression are analyzed and various test data compression techniques are evaluated.