Mathematical Modeling of Clock Binary Tree

Abstract

All the Digital circuits run on clock signal that also makes those circuits synchronous by nature. In a synchronous digital system, clock signal is used to de ne a time reference for the movement of data within that system. The clock distribution network (or clock tree, when this network forms a tree) distributes the clock sig- nals from a common point to all the elements that need it. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the electrical networks used in their distri- bution. Clock signals are often regarded as simple control signals. however, these signals have some very special characteristics and attributes. As clock signal is the only versatile signal thus routing this signal to all the block without skew is tough task. This signal should also have higher driving strength so that it can drive num- ber of modules. Therefore from the origin of clock, there should be a mechanism to increase driving strength with zero skew to reach the RCB (Regional Clock Bu er). Currently for Global clock distribution a structure called clock binary tree with input connected to input and output connected to output of other gates, are used to have minimum skew to complete clock binary tree. This thesis is a compilation of algorithm developed to design clock binary tree and experiments done on di erent tree structures, which are used or can be used in global clock distribution for clock binary tree design.