Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/2414
Title: Medium Frequency Induction Furnace
Authors: Shah, Kajal P .
Keywords: Electrical 2009
Project Report 2009
Electrical Project Report
Project Report
EE (PEMD)
Power Electronics, Machines & Drives
09MEE
09MEE015
PEMD
PEMD 2009
Issue Date: 1-Jun-2011
Publisher: Institute of Technology
Series/Report no.: 09MEE015
Abstract: In recent years, much attention has been focused upon the development of static thyristor inverters to supply high frequency power to induction heating loads. Induc- tion heating can be used for any application where we want to heat an electrically conductive material in a clean, e cient and controlled manner. From the block dia- gram of the whole system, we are required to have voltage and current signals from H-bridge inverter. These signals are then compared with reference signals. Based on the di erence between actual and reference ring of 3-phase full wave recti er is changed.In the same manner voltage across the parallel load is sensed and is com- pared with reference voltage i.e. zero voltage. According to that H-bridge thyristors are red. Thus simulations are performed with the basic circuits. Parallel resonant circuit is placed as a load of H-bridge inverter. Programming is for the ring scheme of H-bridge thyristors and 3-phase full wave recti er.'C' language will be used for programming in ICC AVR.For downloading and debugging AVR STUDIO is to be used.Using IC- CAVR and AVRstudio tools, demo programming has been developed.It is based on single-phase.Power circuit consists of a pair of SCR and diode.The logic remains same with the three-phase.The starting problem is also a typical problem which is to be solved.For that di erent circuits are discussed.The circuit and logic for recti- er has been devloped.The DC current is achieved from 3-phase full wave recti er circuit.Logic has been developed for H-bridge inverter.The current has to be sensed across LC parallel resonant circuit.Flip op logic is generated with the use of OR and AND gate circuit. iv
URI: http://hdl.handle.net/123456789/2414
Appears in Collections:Dissertation, EC (VLSI)

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