Dynamic Partial Reconfiguration of FPGA for SEU Mitigation and Area Efficiency

Abstract

The fast growing VLSI industry demands new techniques for configuring the FPGA. When it comes to defence and space application the configuration of the FPGA becomes more crucial. When it is required to configure the FPGA automatically, the need arises of more sophisticated and fast techniques for reconfiguration of FPGA. In the space application, the effect of radiation changes the bit patterns in the SRAM cells of FPGA, so it is required to put FPGA into its original condition before SEU. Considering all the facts the paper discusses the mitigation techniques for Single Event Upset (SEU) through Dynamic Partial Reconfiguration of FPGA. It is also very useful to save area of the FPGA by reconfiguration. For the proof of concept up and down sampler are developed as a reconfiguration module and then used for Dynamic Partial Reconfiguration technique. The timing and area requirement of reconfiguration using various techniques is the major focus of the paper.