Development of SEU Monitor System for SEU Detection and Correction in virtex-5 FPGA

Abstract

Due to the infrequent and unpredictable nature of real SEUs, small scale testing of their effects and system verification is impractical. For this reason, the SEU controller macro and reference design can emulate an SEU by deliberately injecting an error into the FPGA configuration so that its subsequent detection and correction can be confirmed. Injection of errors can also be used to assess SEU mitigation circuits implemented in a design. We describe the operation and architecture of the proposed logic design as well as its implementation in Xilinx virtex-5 FPGA.