Development of SEU Monitor System for SEU Detection and Correction in virtex-5 FPGA

Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/2798

Title:	Development of SEU Monitor System for SEU Detection and Correction in virtex-5 FPGA
Authors:	Savani, Vijay G. Gajjar, Nagendra
Keywords:	Event Upset (SEU) Internal Configuration Access Port (ICAP) SEU Mitigation Controller Macro EC Faculty Paper Faculty Paper ITFEC024 ITFEC004 NUiCONE NUiCONE-2011
Issue Date:	8-Dec-2011
Publisher:	Institute of Technology, Nirma University, Ahmedabad
Citation:	2nd International Conference on Current Trends in Technology, NUiCONE-2011, Institute of Technology, Nirma University, December 8-10, 2011
Series/Report no.:	ITFEC024-2
Abstract:	Due to the infrequent and unpredictable nature of real SEUs, small scale testing of their effects and system verification is impractical. For this reason, the SEU controller macro and reference design can emulate an SEU by deliberately injecting an error into the FPGA configuration so that its subsequent detection and correction can be confirmed. Injection of errors can also be used to assess SEU mitigation circuits implemented in a design. We describe the operation and architecture of the proposed logic design as well as its implementation in Xilinx virtex-5 FPGA.
URI:	http://10.1.7.181:1900/jspui/123456789/2798
ISBN:	9788192304908
Appears in Collections:	Faculty Papers, EC

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