Test Data Compression Techniques For IP Based SoC : Time, Power and Area Optimization

Abstract

To handle design complexity and short time-to-market, it is increasingly common to use modular design approach in SoC. Such IP cores with hidden architecture have further exaggerated the two burning issues for fabrication testing of SoC: the test cost and test power. The cost of test is strongly related to the increasing test-data volumes which lead to longer test application times and larger tester memory requirement. The solution to this is test data compression. The increasing test power leads to system reliability issues. The dynamic power during scan operations plays a major role in overall test power. This dynamic scan power is directly related to the number of transitions during scan-in and scan-out. Here, the ‘test data compression’ and ‘switching activity reduction’ issues in context of ‘hidden structure of IP cores’ are addressed. In this thesis, various test data compression techniques are surveyed and it was observed that for ATPG generated binary data which contains large number of don’t care bits, ‘run length code’ and ‘statistical code’ based methods are most suitable in context of IP cores. Similarly, the switching activity reduction methods for external testing are suitable to IP cores for power reduction. It was inferred that if the ‘don’t care bit filling’ and ‘reordering’ techniques are used in synergy to pre-process the test data, the compression can be increased and test power can be reduced without much on-chip area overhead. In this thesis, mostly all existing run-length and statistical code methods are implemented and analyzed for compression, power and area overhead. Using the ‘don’t care bit filling’ and ‘reordering’ concepts, the test data processing techniques are proposed to further increase compression and reduce test power. The proposed ‘Run Based Don’t Care Bit Filling’, ‘HDRCBF- DV’, ‘2-D Reordering’ and ‘WTR-CBF-DV’ test data processing techniques are used to improve the run length based test data compression codes. The same way proposed ‘FDBAF’ test data processing technique improves the results for statistical codes. To improve the overall test application time, the ‘Modified Selective Huffman code’ is proposed. Its effectiveness in increasing compression and reducing test application time without any extra area overhead is proved mathematically and also demonstrated with large amount of simulation results.