Low Power and Low Jitter PLL for Clock Generator

Abstract

Low power phase lock loop is becoming necessary for portable and battery operated compact electronic devices, which decreases the risk of reliability problems. So power and jitter have been major big concern in circuit designs from last decade. In this review paper, Several design for PLL have been proposed for low power and low jitter for clock generator circuit. The paper contains the detailed survey on various jitter reduction techniques with low power PLL proposed for clock generator circuit.