Design and Simulation of 3-Stage Pipeline ADC

Abstract

Analog to Digital Converter (ADC) provides the link between the real world of analog signal and the binary digital computational systems. Hence it is needed in all Digital Signal Processing (DSP) applications. Since last few years pipeline ADC architecture become popular in wide range of applications. In this paper, the authors have discussed a 3-stage pipeline ADC architecture using 0.35 μm CMOS technology. The architecture consists of basic blocks like sample and hold, comparator, amplifier, buffer and Digital to analog Converter (DAC). 3-stage pipeline ADC is implemented with lesser number of transistors so it is a low cost implementation. Simulation result of each block as well as each stage is presented which is carried out in Mentor Graphics eldo spice simulator. The layout is carried out in IC station. Power dissipation of the implemented ADC is 5 mW.