Design and Implementation Of RAM Based Shift Register

Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/3312

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DC Field	Value	Language
dc.contributor.author	Vasava, Hiren J.	-
dc.contributor.author	Mehta, Usha	-
dc.date.accessioned	2012-05-25T08:15:25Z	-
dc.date.available	2012-05-25T08:15:25Z	-
dc.date.issued	2009-11-25	-
dc.identifier.citation	National Conference on Current Trends in Technology, NUCONE-2009, Institute of Technology, Nirma University, Ahmedabad, November 25-27, 2009, Page No. 61-65	en_US
dc.identifier.uri	http://10.1.7.181:1900/jspui/123456789/3312	-
dc.description.abstract	High speed applications and technology is becoming an increasingly important and growing area of electronics. This paper describes the design of RAM based shift register in which the data will be shift in left or right as per application requirement and the shifted data output will be stored into the RAM. So here we can easily access the data out, that’s why the speed of the device will become faster than the other techniques.	en_US
dc.publisher	Institute of Technology, Nirma University, Ahmedabad	en_US
dc.relation.ispartofseries	ITFEC010-12	en_US
dc.subject	RAM	en_US
dc.subject	Shift Register	en_US
dc.subject	EC Faculty Paper	en_US
dc.subject	Faculty Paper	en_US
dc.subject	ITFEC010	en_US
dc.subject	NUCONE	en_US
dc.subject	NUCONE-2009	en_US
dc.title	Design and Implementation Of RAM Based Shift Register	en_US
dc.type	Faculty Papers	en_US
Appears in Collections:	Faculty Papers, EC

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