IR @ Nirma University
Keeping in tune the global developments we are creating an institutional repository using DSpace Software (Digital Library Software). We are archiving institutional knowledge like, faculty papers, theses, and dissertations in PDF format at DSpace. Students can access this digital information anywhere in the campus.
Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/3312| Title: | Design and Implementation Of RAM Based Shift Register |
| Authors: | Vasava, Hiren J. Mehta, Usha |
| Keywords: | RAM Shift Register EC Faculty Paper Faculty Paper ITFEC010 NUCONE NUCONE-2009 |
| Issue Date: | 25-Nov-2009 |
| Publisher: | Institute of Technology, Nirma University, Ahmedabad |
| Citation: | National Conference on Current Trends in Technology, NUCONE-2009, Institute of Technology, Nirma University, Ahmedabad, November 25-27, 2009, Page No. 61-65 |
| Series/Report no.: | ITFEC010-12 |
| Abstract: | High speed applications and technology is becoming an increasingly important and growing area of electronics. This paper describes the design of RAM based shift register in which the data will be shift in left or right as per application requirement and the shifted data output will be stored into the RAM. So here we can easily access the data out, that’s why the speed of the device will become faster than the other techniques. |
| URI: | http://10.1.7.181:1900/jspui/123456789/3312 |
| Appears in Collections: | Faculty Papers, EC |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ITFEC010-12.pdf | ITFEC010-12 | 175.18 kB | Adobe PDF |  View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.