Design and Implementation Of Three Level Inverter Using DSP

Abstract

Three level voltage-fed inverters have gained importance in high power high performance industrial drive applications. Neutral point clamped (NPC) power topology mostly used for threelevel inverter. Neutral point clamped (NPC) topology has problem of DC-link capacitor voltage balancing. It can be solved using self-balancing SVPWM scheme, and closed loop capacitor voltage balancing scheme. The report explains different Multilevel Inverter topologies such as Neutral point clamped Inverter, Flying Capacitor Inverter, and H-Bridge Cascaded Inverter. Two modulation methods – Sinusoidal PWM (SPWM) and Space Vector PWM (SVPWM), used in Multilevel Inverters are explained in this report. The pulse based dead time compensation method for three-level inverter is also discussed in this thesis. The PSIM simulation results of SPWM and SVPWM are included in this report. The Verification of SVPWM algorithm using PSIM Simulation, Code Composer Studio and R-C Low pass filter with DSP (TMS320F2811) Control Card are included in the report. This report includes experimental results of three-level inverter and two-level inverter for various conditions. Experimental results prove ability of self-balancing SVPWM scheme and pulse based dead time compensation scheme for stable operation. Finally, the THD analysis between three-level and two-level inverter are discussed in this report. Index Terms: Neutral point clamped (NPC) Topology, Pulse Based Dead Time Compensation, SVPWM and Three-Level Inverter.