Analysis And Usage Of Formal Equivalence Check On SoC

Abstract

Ever-growing complexity in System on Chip (SOC) is forcing logic design to move above the register transfer level (RTL). For example, functional speci cations are being written in software. These speci cations are written for clarity, and are not optimized or intended for synthesis. The Logic Synthesis as a process is prone to Bugs. There are too many transformations happening in logic synthesis which can alter the netlist in a wrong manner and make it infer functionality other than what was intended in the original RTL. These bugs are not intentional but happen by accident during synthesis tool development. So Functional Equivalence Veri cation (FEV) between the software speci cation and the implementation is needed. This report introduces the Functional Equivalence Veri cation approach for SOC. It describes the method for functional equivalence veri cation. It also introduces the algorithm by which the FEV tool runs. This report imposes upon the importance of the Formal Equivalence Veri cation in VLSI design Flow.