Automation of I/O ring design and logic realization

Abstract

Manual design can occur with small number of transistors. As number of transis- tors increase through VLSI design, the amount of evaluation and decision making has become overwhelming. Computer-aided Design (CAD) tool automates this whole process, hence it reduces TTM (Time To Market). CAD tools allow large and com- plex problems to be solved. CreateChipIOLogic (CCIOL) is a CAD tool, which is used to generate padring, insert BSR (Boundary Scan Cell) at RTL level and gen- erate IO Muxing logic. Output le of this tool is a Verilog le. As per the required speci cations of the di erent projects at STMicroelectronics, new functionalities are added in the tool. Hence, Regression Testing plays important role to check whether the previously tested tool code runs correctly or not and the added functionality has not negatively impacted any functionality that it o ered previously. Regression test- ing steps (I) Make test plans and create test cases for CreateChipIOLogic tool (II) Check generated output logic corresponding di erent inputs. (III) Check syntax of generated Verilog le using ncsim (Cadence) tool. (IV) Check equality of di erent hierarchy structures by using Formality (Synopsys) tool. (V) Check generated code is synthesizable or not by using Design compiler (Synopsys) and Spyglass tool.