Low Power RTL Design and RTL Quality Check

Abstract

The project combines the various sensor together.For this purpose we require communication between GPIO,IP's and CHIP core so we have to build a block which will allow to communicate these three blocks with each other.So I have designed the block called DATAPATH SELECTION MODULE .It will allow to operate the GPIO in I/O mode ,normal mode and functional mode.The RTL design is in verilog and it is successfully veri ed and synthesized. Also the project contains RTL quality check which checks the quality of RTL code that follows the certain rules according to LANGUAGE REFERENCE MANUAL.In this project I performed the LINTRA on each of the partition and on top RTL.I report all the error and warnings to a designer and xed error and warning which a ect the design quality.By doing the LINTRA on RTL design it is easy to synthesize the design. UPF is designed to re ect the power intent of a design at a relatively high level. UPF scripts describe which power rails should be routed to individual blocks, when blocks are expected to be powered up or shut down, how voltage levels should be shifted as signals cross from one power domain to another and whether measures should be taken to retain register and memory-cell contents if the primary power supply to a domain is removed.When the blocks are power down how to apply the isolation ?All these low power related issue can be solved using UPF.