Optimization In Timing Analysis Corners In 28nm

Abstract

Static Timing Analysis (also referred as STA) is one of the many techniques available to verify the timing of a digital design. An alternate approach used to verify the timing is the timing simulation which can verify the functionality as well as the timing of the design. The term timing analysis is used to refer to either of these two methods - static timing analysis, or the timing simulation. Thus, timing analysis simply refers to the analysis of the design for timing issues. The STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pins. This is in contrast to simulation based timing analysis where a stimulus is applied on input signals, resulting behavior is observed and veri ed, then time is advanced with new input stimulus applied, and the new behavior is observed and veri ed and so on. The purpose of static timing analysis is to validate if the design can operate at the rated speed. To simulate and verify all timing conditions of a design with 10-100 million gates is very slow and the timing cannot be veri ed completely. Thus, it is very di cult to do exhaustive veri cation through simulation. In this project Timing Analysis is done to identify and diagnose the violation in complex design, learn to perform synthesis for the giver RTL using synopsys tool DC(DESIGN COMPILER), STA using synopsys tool PT(PRIMETIME) tool, which Setup and hold violations in complex design. Formal veri cation is done by the synopsys tool called formality.