Evaluation of specific features of CAD tool (APACHE) for CMOS Standard Cell Flow

Abstract

With technology scaling, the trend for high performance integrated circuits is towards higher operating frequency, lower power supply and lower power dissipation. Lower supply voltage leads to smaller noise margins and less tolerance for voltage drop (for average voltage drop and more so for dynamic voltage drop). As design houses move their designs to sub-micron technologies, the need for dynamic voltage drop (or DvD) verification has become a sign-off requirement prior to tape-out. This project evaluates the specific features of APACHE tool for CMOS Standard Cell flow and IR-drop for full chip cell based power/ground Design. Apache Power Library (APL) is the solution of Library characterization using SPICE simulation which is used in Redhawk Dynamic analysis in APACHE. Because the APL characterized data are more realistic for Dynamic IR Analysis, so as a Library provider we want to do some modification in existing Characterization Flow and integrate APL methodology with them. So first we understand the APL methodology and then update present flow to align and support the APACHE flow. Calculate the IR drop of a Design through Apache’s Redhawk, and see the effect of APL characterized data in voltage drop, so the intrinsic and extrinsic de-cap are used in fixing the design.