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http://10.1.7.192:80/jspui/handle/123456789/4004
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DC Field | Value | Language |
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dc.contributor.author | Patel, Usha | - |
dc.date.accessioned | 2013-11-22T09:17:14Z | - |
dc.date.available | 2013-11-22T09:17:14Z | - |
dc.date.issued | 2013-06-01 | - |
dc.identifier.uri | http://10.1.7.181:1900/jspui/123456789/4004 | - |
dc.description.abstract | In most electronic imaging applications, images with high resolution are desired and often required. High resolution means that pixel density within an image is high, and therefore an HR image can offer more details that may be critical in various applications. Real time image super resolution is the ability to perform super resolution on a set of input frames at a higher rate. However as FPGA’s have grown in capacity, improved in performance and decreased in cost they have become a viable solution for performing computationally intensive task with the ability to tackle applications for custom chips and programmable DSP devices. Though this involves intensive research on the hardware implementation of super resolution algorithm. This project work is mainly based on implementing video super resolution algorithms in FPGA and come up with an effective embedded solution. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 10MCES05 | en_US |
dc.subject | Split | en_US |
dc.subject | Split 2010 | en_US |
dc.subject | CE Split | en_US |
dc.subject | CE Split 2010 | en_US |
dc.subject | Computer 2010 | en_US |
dc.subject | Project Report 2010 | en_US |
dc.subject | Computer Project Report | en_US |
dc.subject | Project Report | en_US |
dc.subject | 10MCE | en_US |
dc.subject | 10MCES | en_US |
dc.subject | 10MCES05 | en_US |
dc.title | Real Time Super Resolution | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, CE |
Files in This Item:
File | Description | Size | Format | |
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10MCES05.pdf | 10MCES05 | 3.28 MB | Adobe PDF | ![]() View/Open |
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