Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/4004
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dc.contributor.authorPatel, Usha-
dc.date.accessioned2013-11-22T09:17:14Z-
dc.date.available2013-11-22T09:17:14Z-
dc.date.issued2013-06-01-
dc.identifier.urihttp://10.1.7.181:1900/jspui/123456789/4004-
dc.description.abstractIn most electronic imaging applications, images with high resolution are desired and often required. High resolution means that pixel density within an image is high, and therefore an HR image can offer more details that may be critical in various applications. Real time image super resolution is the ability to perform super resolution on a set of input frames at a higher rate. However as FPGA’s have grown in capacity, improved in performance and decreased in cost they have become a viable solution for performing computationally intensive task with the ability to tackle applications for custom chips and programmable DSP devices. Though this involves intensive research on the hardware implementation of super resolution algorithm. This project work is mainly based on implementing video super resolution algorithms in FPGA and come up with an effective embedded solution.en_US
dc.publisherInstitute of Technologyen_US
dc.relation.ispartofseries10MCES05en_US
dc.subjectSpliten_US
dc.subjectSplit 2010en_US
dc.subjectCE Spliten_US
dc.subjectCE Split 2010en_US
dc.subjectComputer 2010en_US
dc.subjectProject Report 2010en_US
dc.subjectComputer Project Reporten_US
dc.subjectProject Reporten_US
dc.subject10MCEen_US
dc.subject10MCESen_US
dc.subject10MCES05en_US
dc.titleReal Time Super Resolutionen_US
dc.typeDissertationen_US
Appears in Collections:Dissertation, CE

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