Design and Simulation of 2.4 GHz Frequency Synthesizer

Abstract

A PLL( Phase locked loop) is a closed loop frequency system that locks the phase of an output signal to an input reference signal. The term lock refers to a constant or zero phase difference between two signals. The signal from the feedback path, ffb, is compared to the input reference signal, Fref , until the two signals are locked. If the phase is unmatched, this is called the unlocked state, and the signal is sent to each component in the loop to correct the phase difference. These components consist of the Phase Frequency Detector (PFD), Charge pump (CP) Low pass filter (LPF) and Voltage controlled oscillator (VCO). and Frequency Divider. The PFD detects any phase differences in Fref and ffb and then generates an error signal. According to that error signal the CP either increases or decreases the amount of charge to the LPF. This amount of charge either speeds up or slows down the VCO. The loop continues in this process until the phase difference Fref. and ffb is zero or constant this is the locked mode. After the loop has attained a locked status, the loop still continues in the process but the output of each component is constant. The output signal, fout, has the same phase and or frequency as Fref. PLLs ( Phase Locked Loop) are commonly used in communications systems in wireless application and wireless sensor The frequency synthesizer is designed to operate using a reference signal 20 MHz producing an output signal 2.4 GHz A1.8 V CMOS 2.4 GHz frequency synthesizer with low phase noise and power is presented. Low power consumption and phase noise is achieved by using a Current Starved VCO. The synthesizing frequencies 2.4GHz The divider network is designed using dynamic true single-phase logic (TSPC) for low power operation. The 2.4GHz frequency synthesizer is designed using 0.18µm TSMC CMOS 1P6M Technology.