Development of Verification IP for LINFlex Controller using UVM

Abstract

With increasing complexity of IP-Core based SoC Design, it is important to select proper verification methodology that offer best possible performance and required least effort to setup and debug verification environment. Traditional module based verification methodology which combines both environment and tests. It's required to modify environment when writing a new test. Work embodied in the thesis presents the development of Verification IP for LINFlex Controller using UVM. Verification IP consists of all standard components Driver, Monitor, Scoreboard, Agent and top environment. UVM based methodology separates environment and tests so each test will configure environment as per its need. Sequence library and tests has been developed for a particular SoC for the verification of LINFlex Controller. Verification IP has been developed in such a manner it can be plugged to SoC level verification testbench.