Parametrization of SRAM sub-system

Abstract

Creating reusable models typically requires that general-purpose models be written with re-definable parameters such as SIZE, WIDTH and DEPTH. With respect to coding parameterized Verilog models, two Verilog constructs that are over-used and abused are the global macro definition (`define) and the infinitely abusable parameter redefinition statement (defparam). This report will detail techniques for coding proper parameterized model for SRAM Controller, detail the differences between parameters and macro definitions, present guidelines for using macros, parameters, parameter definitions and also some added features in existing design with RTL quality check like Lintra and LEC on whole design for making it easy to synthesize. And also verifying the updated design by creating new test case which will mostly concentrating on verification of updated features in the design.