Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/417
Title: | 4096 Pixel Linear CCD Visible Imager and Development Of Switched Capacitor Amplifier For ROIC |
Authors: | Reddy, G. Venkata Penchala |
Keywords: | EC 2003 Project Report 2003 EC Project Report Project Report 03MEC 03MEC005 VLSI VLSI 2003 |
Issue Date: | 1-Jun-2005 |
Publisher: | Institute of Technology |
Series/Report no.: | 03MEC005 |
Abstract: | This REPORT is basically divided into two parts. The first part is about 4096 pixels linear CCD visible imager. This part contains introduction to imaging systems. Electronic imaging systems based on solid-state image sensors have received tremendous attention in the past few years. The many advantages of the sold-state image sensors have opened up a wide variety of new imaging possibilities applications, ranging from high resolution, space borne electronic camera to PC peripheral camera, were costly, if not possible, using earlier technology. This part will explains the basic theory of CCD, CDS, pre-amplifier, ADC, design of architecture that converts the four shift registers pixel output data of CCD into single line of data using VHDL and lastly interfacing of FPGA output to PC using serial port (RS232). The second part is about Development of Switched Capacitor Amplifier for an ROIC. This is about analysis and design of op-amp & thereafter offset compensated Switched Capacitor (SC) amplifier which is one of the functionality needed in development of Readout Integrated Circuit (ROIC). The implementation of active pixel based image sensors in CMOS technology is becoming increasingly important for producing imaging systems that can be manufactured with low cost, low power, simple interface, and with good image quality. The major obstacle in the design of CMOS imagers is Fixed Pattern Noise (FPN) and Signal-to-Noise-Ratio (SNR) of the video output. This part will explains the basic introduction to CMOS sensor, description about block diagram of Read Out Integrated Circuit (ROIC), integration and operating modes of ROIC. This part also contains buffer design with load of 10PF using two stage operational amplifier and Autozeroing (offset compensation) Technique implementation using non-inverting and inverting Switched Capacitor voltage amplifier circuits. The use of offset compensated switched capacitor amplifier removes the effect of unpredictable offset, which develop in amplifier after fabrication. |
URI: | http://hdl.handle.net/123456789/417 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
03MEC005.pdf | 03MEC005 | 1.88 MB | Adobe PDF | ![]() View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.