Verification Of A Chip Block at Module and Board Bringup Level

Abstract

With gate counts and system complexity growing exponentially, engineers confront the most perplexing challenge in chip design cycle: Verification. Verification of the design RTL is done at various phases of the chip design flow at different abstraction levels. The Major Project “The Verification Of A Chip Block At Module and Board Bringup Level” concentrates on two types of Functional Verification at different stages in the Chip Design Flow. During Design phase, verification is done at low abstraction level, concentrating on the core functionality of the module. The inputs to the module are forced through the testbench and its interfaces are not looked upon. This is the functional verification of chip at module level and is done at the RTL design phase. After the RTL is been finalized after fixing all the bugs, it is send to the fabrication unit. The first chip that will tap out from the fabrication unit has to be tested on the operational board for it. The verification engineers work on the development of simulation platform for verifying each module of the chip for its functionality and dataflow within and external to the chip. The test cases developed for this, once pass on the bringup simulation platform, will be executed by the first chip on the board. The abstraction level is high and concentration is on the interfaces. The modules called MI (Mate Ingress) and ME (Mate Egress) are verified for functional verification at module level. The Verification Environment Serving as Platform for simulation is developed with C++ and Verilog. The Test Bench is in Verilog and instantiates two modules Mate Ingress and Mate Egress that are interfaced internally. The module is thoroughly verified which different combinations of input streams generated by Standard SONET frame generator. The same Standard SONET frame analyzer is used to verify the output from the Design under Test. The test cases required to exercise the module for its core functionality are written and simulated as per the test plan. As the verification progressed, different issues related to Verification Environment, Test Bench, Test Case and RTL arouses. The RTL issues are filed as bugs and get resolved by the designers. This results in updation of all the verification components as per requirement. After passing all the test cases, the code coverage is done and based on it new test scenarios are added. The module called EC (Enhanced Co-processor) is verified for functional verification at board bringup level. This module is a co-processor to a Video Processor and performs complex computational tasks for it. The flow starts with preparation of Test Plan for the bringup verification. The next step is to develop the bringup verification environment. This platform for simulation considers the complete data path for the module under test. It mimics the actual scenario the module will face when the chip is operational on the board. The development of test cases as per the test plan follows. Test cases are written to test each instruction in each operational mode along the complete data path. The chip on board exercises the pass test cases.