IR @ Nirma University
Keeping in tune the global developments we are creating an institutional repository using DSpace Software (Digital Library Software). We are archiving institutional knowledge like, faculty papers, theses, and dissertations in PDF format at DSpace. Students can access this digital information anywhere in the campus.
Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/4303| Title: | Validation of Next Generation Intel Xeon Processor in Coverage Collection, Memory Matrix and Optimization |
| Authors: | Patel, Ronak M. |
| Keywords: | EC 2011 Project Report Project Report 2011 EC Project Report EC (Communication) Communication Communication 2011 11MECC 11MECC12 |
| Issue Date: | 1-Jun-2013 |
| Publisher: | Institute of Technology |
| Series/Report no.: | 11MECC12 |
| Abstract: | Post-Silicon environment is a tremendous challenge as the design complexity is increasing with next generation processors. The aim of this project is to analyze several coverage points, collect various coverage data samples across di erent soft- ware/hardware combinations, write test cases on various memory risers and validate di erent types of combinations in memory matrix. At last, some automation in cov- erage collection and memory matrix both is also incorporated. |
| URI: | http://10.1.7.181:1900/jspui/123456789/4303 |
| Appears in Collections: | Dissertation, EC (Communication) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 11MECC12.pdf | 11MECC12 | 1.65 MB | Adobe PDF |  View/Open |
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