Power Analysis of I/O Cells

Abstract

Two bottle-necks for today’s IC designers are speed and power. Moreover, there is trade of between the two. In today’s world of mobile devices low power is one of the major requirements. In this thesis are carried out, some of the power analysis on I/Os, which are one of the major components responsible for the power consumption. Entire power characterization is divided into to parts, static and dynamic power. Leakage power or static power is the power dissipated by the cell when it is not switching, that is, when it is inactive or static. The largest percentage of static power results from source-to-drain sub threshold leakage. This leakage is caused by reduced threshold voltages that prevent the cell from completely turning off. Static power is also dissipated when current leaks between the diffusion layers and the substrate. Internal power is any power dissipated within the boundary of a cell. During switching, a circuit dissipates internal power by the charging or discharging of any existing capacitances internal to the cell. The definition of internal power includes power dissipated by a momentary short circuit between the P and N transistors of a cell, called short circuit power. For circuits with fast transition times, short circuit power can be small. However, for circuits with slow transition times, short circuit power can account for 30 percent of the total power dissipated by the gate. Short circuit power is also affected by the dimensions of the transistors and the load capacitance at the gates output. In this thesis work, different component of currents responsible for leakage and internal power are analyzed for different temperature, voltage, slope and load conditions. Also, the analysis of different I/O cells for Leakage Power and Internal Energy are carried out for different parametric variations.