Architecture Evaluation for Programmable Logic in 65NM

Abstract

A plurality of Electronically Reconfigurable Gate Array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigurable interconnect permits the digital network realized on the interconnected circuits to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA circuits dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic circuits. In STMicroelectronics we divide the programmable logic in two part software and hardware. Software part includes development of software for the use of PiCoGA architecture and hardware part includes development of different libraries in 90nm and 65 nm for the realization of that architecture. Work carried out in this group was to prepare complete library set which includes all basic functionality in 65nm technology using Structured ASIC.