Automation of IP Qualification Test Vehicle Verification Environment

Abstract

Purpose of Testchip is to verify the invented Technology and IPs added in SOC which implementation in silicon wafer possibility. It includes all the IPs which are to be used for Researched Technology or SOC applications. Testchip provides post silicon validation details included Library of Memory, RO, Standard-Cell, Analog or any other IP. A test chip implemented in the FDSOI 28nm process is designed and fabricated, containing numerous test structures aimed of testing silicon functionality and investigating process variation. Scan chain and Boundary scan are inserted for better testing capability.

Before any SOC/ASIC Mass Productions, Test Chip gives us better silicon pa-rameters and testability. It makes such structure that testing made easy and less time consuming. It included BIST and BISC which are used for Testing and Charac-terizing chip itself automatically. BIST (Build In Self Test) include the logic of the memory testing algorithm of memory, by setting up the some of the internal register pins. BISC (Built In Self Characterization) used for Setup Time Characterization, Maximum Frequency Characterization, Access Time Characterization of chip.

Test Patterns are similar to test vectors except these are cycle based patterns. Patterns for the testing are deliver to the Fabrication after the tape-out. These Patterns are almost same except which IP are being tested so that I have responsibility to make these patterns automatically generated. Fulfillments of this tool give better quality of test patterns, accurate and less time consuming to generate. It also helps in quick verification of RTL/netlist of any block or while chip. This thesis presents a test chip methodology and automatic generation of test pattern to help achieve these fundamental goals.