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Title: | Standard Cell Characterization And Packaging |
Authors: | Ardeshana, Gauravkumar P. |
Keywords: | EC 2012 Project Report Project Report 2012 EC Project Report EC (VLSI) VLSI VLSI 2012 12MEC 12MECV 12MECV33 |
Issue Date: | 1-Jun-2014 |
Publisher: | Institute of Technology |
Series/Report no.: | 12MECV33; |
Abstract: | Standard cells are basic building blocks for ASIC (Application-Specific Integrated Circuit) design. Semi-custom design flows are a key factor for the rapid growth of integrated circuits and systems. They lower the design complexity through the use of pre-designed and pre-characterized functional components called standard cells, instead of assuming that designers have to draw, place and connect each transistor. Cell Characterization is the process of simulating a standard cell with a spice simulator (like ELDO) and an automated characterization tool to extract this information and convert into a format that other tools can utilize. Using spice ELDO (Mentor Graphics tool) simulator timing, power & noise information is extracted for each cell. All this data has to be consolidated in a library (in Synopsys Technology Format) along with some important views & documentation in form of a package. The libraries are used by synthesis tools for extracting gate level netlist of the digital circuit from RTL level design & these are also used in place and route tools. In the initial phase of my dissertation work, I understood the working of tools (like ELDO, Automatic Library Tool etc.) and the flow for characterization & packaging. I will also learn the methodologies used to evaluate timing, power, constraints & noise parameters. In the second phase, standard cell characterization & packaging will be done for nanometer Technology designs for different libraries. The impact of various parameters such as Threshold voltage, Process, Temperature, Drive Strength, Body Biasing and Gate Length on standard cell is analyzed. The prime focus in this work is firstly to characterize (extract timing, power, noise information) set of standard cells at various PVT (Process, Voltage, Temperature) corners for a fixed set of input slopes & load capacitances and compare it with previous technology, secondly to consolidate the characterized data of each cell in a .lib (Synopsys Technology Format) also including some important views (Back end, Front end, Packaging, etc.) in a package that is later used by SOC designers. |
URI: | http://hdl.handle.net/123456789/4724 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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12MECV33.pdf | 12MECV33 | 2.07 MB | Adobe PDF | ![]() View/Open |
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