Enablement of Optimal and Fast Timing Convergence for High speed I/O Designs

Abstract

The ASIC devices are often composed of third-party IP (Intellectual Property), custom or semi-custom functional blocks, fab-vendor memory macros, standard cell logic, etc. As design sizes increase and customers migrate to static timing analysis solutions that incorporate delay calculation using parasitic information and signal integrity analysis, capacity and runtime issues for full-chip analysis becomes increasingly important.

For Static Timing Analysis, timing abstractions of designs for complex blocks or IP blocks can improve capacity and runtime while preserving reasonable accuracy. Usually, the digital blocks of an IP are modeled into a library and analog parts are used as it is for timing analysis. This report addresses the issue and implementation of bounding the analog modules of an IP into a timing model or a Liberty Syntax. For the design convergence, making the flows optimal is required. The effect of variation is observed on the design parameters.