Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/4727
Title: Design & Analysis of SRAM Memory Compiler & its Characterisation
Authors: Selani, Yusuf
Keywords: EC 2012
Project Report
Project Report 2012
EC Project Report
EC (VLSI)
VLSI
VLSI 2012
12MEC
12MECV
12MECV30
Issue Date: 1-Jun-2014
Publisher: Institute of Technology
Series/Report no.: 12MECV30;
Abstract: This Project Report explores the Analysis, Post-Layout Extraction, Set-up development, Design-validations and Cut-Generation of Single port Static Random Access Memories (SRAM) & Read only memory (ROM) with 90 nanometer three Metal layer Technology. The SRAM characterization includes various measurements like timings & capacitances. Validation includes the analysis of performance aspects of Memory Cell, Verification of functionality by applying Tight Stimuli which is generated by timing values, Marginality Analysis; Write through Analysis, Power-On Reset Analysis, Sense-Amp-Offset Analysis, Self-time Read Analysis, Self-time Write Analysis, Latch Analysis, Sense-Pulse-Width Analysis. CUT generation is done for providing the Specification of a memory cut through a Graphical User Interface on WebGen. I investigate the methodology of characterization of the parameters and validation of functionality.
URI: http://hdl.handle.net/123456789/4727
Appears in Collections:Dissertation, EC (VLSI)

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