Study of Electro Migration in Full Custom ASIC Design and Develop Assessment Methodology

Abstract

The electro migration effect within current-density-stressed signal and power lines is an important reliability and design problem in sub-micron IC designs. It is therefore necessary to consider electro migration-related design parameters as early as possible in the physical design flow. With technology scaling down for integrated circuits, electro-migration (EM) has become a serious chronic pitfall under deep sub-micron process. It not only affects power distribution network, but also impart impact on clock/signal interconnection. So clock/signal EM deserves more attention. In principle, EM violations are caused by high current density which is related to routing width, metal width and length, operating frequency, operating temperature, transition, load and so on. These factors affect with each other and determine the performance of the IC. This project based on to develop methodology to predict electro-migration in Memory Compiler. Firstly, detailed analysis of each factor related to clock/signal EM is done. Secondly, based on IC Compiler architecture, some methods are proposed to predict clock/ signal EM violations based on certain corner data present in database. We have mathematically modeled dependency of electro-migration on various physical and operating parameters to predict the EM violation of any Memory instance belongs to similar architecture by using VBA environment.